(1) Field of the Invention
The present invention relates to a transfer gate circuit for reliably transferring an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of a single transfer gate transistor.
(2) Description of the Related Art
Generally, a transfer gate circuit of this kind comprises CMOS type transfer gate transistors including a P-channel type transistor and an N-channel type transistor connected in parallel. The gates of the P-channel type transistor and the N-channel type transistor are supplied with a control clock signal and its inverted signal, respectively. When the above pair of transistors are turned on in accordance with the potential levels of the control clock signal and its inverted signal supplied thereto, an input signal supplied to the input side of the CMOS type transfer gate transistors is transferred to the output side thereof.
Here, the reason why the transfer gate circuit comprises the above pair of transistors constructed in the CMOS form, is that if the transfer gate were comprised only of the P-channel transistor, in the low level (zero level) state of the input signal, the potential of the output side would not fall below the threshold voltage of the P-channel transistor and if the transfer gate were comprised only of the N-channel transistor, in the high level (e.g., V.sub.CC1 level) state of the input signal, the potential of the output side would not rise above the value of the high level potential of the inverted control clock signal minus the threshold voltage of the N-channel transistor. On the other hand, by constructing the transfer gate in the above CMOS form, the low level and high level of the input signal can be transferred as they are to the output side in accordance with the potential level of the control clock signal. Note that the above high level potential V.sub.CC1 of the input signal is produced through an inverter circuit, for example.
When the above pair of CMOS transistors are formed in a P-type substrate, for example, source and drain regions of the N-channel transistor are formed in the above P-type substrate, and also, source and drain regions of the P-channel transistor are formed in an N-type well formed in the P-type substrate. The input signal having the potential V.sub.CC1 in the high level side is supplied to one of the source (drain) regions of each of the N-channel and the P-channel transistors, and the above input signal is taken out as the output signal from the other source (drain) region of each of the N-channel and the P-channel transistors. Note that the N-type well in which the P-channel transistor is formed is supplied with a predetermined potential V.sub.CC2 (as mentioned later, which is lower than V.sub.CC1) from a power supply line which is common with the above inverter circuit.
As mentioned above, the N-type well in which is formed the P-channel transistor comprising the CMOS type transfer gate is supplied with the predetermined potential V.sub.CC2 from the power supply line which is common with a circuit for production of the input signal to be transferred (e.g., the inverter circuit), but the power supply line inevitably includes a wiring resistance. Particularly, if some circuits belonging to another system, for example, are provided between the inverter circuit and the above transfer gate transistors, the length of the power supply line between the inverter circuit and the transfer gate transistors becomes relatively long, and thus, the value of the wiring resistance due to the above length of the power supply line becomes relatively high. Further when the power current is supplied to some peripheral circuits provided on the same substrate through the power supply line, the value of the power current flowing through the power supply line also becomes high. Therefore, in such a case, a relatively large potential difference occurs between the potential V.sub.CC1 supplied from the power supply line to the inverter circuit and the potential V.sub.CC2 supplied from the power supply line to the N-type well. The potential V.sub.CC2 therefore becomes lower than the potential V.sub.CC1 (that is, V.sub.CC1 &gt;V.sub.CC2).
On the other hand, as a current (i.e., the input signal) flowing through a signal line is small, the high level potential of the input signal supplied to the transfer gate transistors is nearly equal to the high level potential V.sub.CC1 supplied from the inverted circuit, so in the high level state of the input signal, a PN junction turns on between the source (drain) of the P-channel transistor to which the potential V.sub.CC1 is supplied and the N-type well to which the potential V.sub.CC2 is supplied. Due to this, there is a chance of occurrence of so-called latch-up by the thyrister equivalently comprised by the PNPN layers formed in the above P-type semiconductor substrate. In such a case, subsequent to this, there is the problem that current will continue to flow in the semiconductor substrate through the PNPN layers.